A Unified Architecture for AES/PRESENT Ciphers and its Usage in an SoC Environment
IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani
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Title |
A Unified Architecture for AES/PRESENT Ciphers and its Usage in an SoC Environment
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Creator |
Pandey, JG
Gupta, S Karmakar, A |
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Subject |
IC Design
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Description |
Electronic data security is of vital concern for secure
communication applications of cyber-physical system (CPS) that relies on Internet-of-things (IoT) based technologies. To achieve multi-level data security, a combination of long-term secure cipher, advanced encryption standard (AES), and short-term secure cipher, PRESENT are deployed together for forming a common cipher chip. The core is used for secure audio application
in an open source system-on-chip (FPGA-SoC) environment.
An integrated implementation of the cores is done on FPGA-SoC and ASIC. FPGA implementation of the architecture on Xilinx xc5vlx110t-1-ff1136 FPGA device consumes 14% slices. Further, the design is implemented in SCL 180 nm CMOS ASIC technology, it takes 2 x 2 mm2 die size containing 0.867 mm2 standard cell area. At 100 MHz clock frequency, total power consumption of the chip is 11.9 mW.
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Date |
2020
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Type |
Conference or Workshop Item
PeerReviewed |
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Format |
application/pdf
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Identifier |
http://ceeri.csircentral.net/538/1/412019%281%29.pdf
Pandey, JG and Gupta, S and Karmakar, A (2020) A Unified Architecture for AES/PRESENT Ciphers and its Usage in an SoC Environment. In: 11th IEEE Latin American Symposium on Circuits and Systems (LASCAS-2020), February 25-28, 2020, San Jose, Costa Rica. |
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Relation |
http://ceeri.csircentral.net/538/
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